The present disclosure relates to an apparatus and method for transmitting/receiving a signal in a communication system, and more particularly, to an apparatus and method for transmitting/receiving a signal in a communication system supporting a bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme.
To meet the demand for wireless data traffic, which has increased since deployment of 4th-generation (4G) communication systems, efforts have been made to develop an improved 5th-generation (5G) or pre-5G communication system. Therefore, the 5G or pre-5G communication system is also called a ‘beyond 4G network’ or a ‘post long-term evolution (LTE) system.’
It is considered that the 5G communication system will be implemented in millimeter wave (mmWave) bands, e.g., 60 GHz bands, so as to accomplish higher data rates. To reduce propagation loss of radio waves and increase a transmission distance, a beam forming technique, a massive multiple-input multiple-output (MIMO) technique, a full dimensional MIMO (FD-MIMO) technique, an array antenna technique, an analog beam forming technique, and a large scale antenna technique are discussed in 5G communication systems.
In addition, in 5G communication systems, development for system network improvement is under way based on advanced small cells, cloud radio access networks (RANs), ultra-dense networks, a device-to-device (D2D) communication, a wireless backhaul, a moving network, a cooperative communication, coordinated multi-points (CoMP), reception-end interference cancellation, and the like.
In the 5G system, a hybrid frequency shift keying (FSK); quadrature amplitude modulation (QAM) modulation (FQAM); a sliding-window superposition coding (SWSC) (e.g., as an advanced coding modulation (ACM) scheme); a filter bank multi carrier (FBMC) scheme, a non-orthogonal multiple Access (NOMA) scheme, and a sparse code multiple access (SCMA) scheme (e.g., as an advanced access technology) have been developed.
Communication systems have evolved to support a high data rate to satisfy wireless data traffic demand. For example, such communication systems have evolved to enhance spectral efficiency and increase channel capacity to increase data rate employing various communication schemes, such as an orthogonal frequency division multiplexing (OFDM) scheme, a multiple-input/multiple-output (MIMO) scheme, and the like.
Cell-edge user equipments (UEs) face situations in which a signal-to-noise ratio (SNR) is low at a cell edge region (which is far from a cell center), or in which a carrier-to-interference and noise ratio (CINR) is low due to great interference from a base station (which is located at a neighbor cell). Such situations may be a factor that may degrade total system performance of the communication system. As a result, certain communication systems have developed various schemes to increase transmission efficiency for cell-edge UEs, e.g., an inter-cell interference-coordination (ICIC) scheme, a coordinated multi-points (CoMP) scheme, an interference cancellation scheme, and the like.
BICM-ID scheme is another scheme that may support a high data rate by increasing channel capacity. The BICM-ID scheme will be described below.
In a coded modulation (CM) system, a typical approach is a scheme of using an interleaver to decrease bit correlation relation between a channel code and a mapper. Performance of the interleaver may be determined according the following two elements.
The first element that may affect performance is hardware complexity. Generally, an interleaver performs an operation of changing an order of input bits. As the number of the input bits increases, the size of the interleaver increases and in turn, the hardware complexity increases. The number of the input bits which are input to the interleaver needs to be considered on designing the interleaver.
The second element that may affect the performance of the interleaver is error rate. In certain communication systems, the BICM-ID scheme may have a function similar to an error correction code. As such, an interleaver configuration that has a low error rate becomes an important factor for enhancing total system performance. However, as described above, if the number of input bits which are input to the interleaver is increased, the interleaver size is increased as well.
Generally, a random interleaver has the best error rate performance. Performance of a random interleaver depends on knowing which one among all input bits is input at related input location. The random interleaver requires information on all of N input bits, from 1 to N, upon inputting an input signal of a length N, i.e., an input signal including the N input bits. However, since such random interleavers require information on all input bits, hardware complexity is increased and total system throughput is decreased.
So, even though the random interleaver has the best performance, it is difficult to implement the random interleaver due to hardware complexity in a practical communication system. Various studies for an interleaver with decreased hardware complexity and good performance have been in development.
A typical interleaver of this sort is a block interleaver. The block interleaver will be described below.
The block interleaver has a structured characteristic. The block interleaver may store a structure of the block interleaver using a relatively small amount of information. Specifically, one integrated interleaver may be designed using a plurality of block interleavers. In this case, each of the plurality of block interleavers may be regarded as a structured interleaver.
The integrated interleaver has a form similar to a random interleaver. The performance of the integrated interleaver is similarly good.
However, it may be difficult to implement such integrated interleaver for several reasons. First, while the integrated interleaver has short processing delay time compared to a conventional random interleaver, the integrated interleaver still has long processing delay time. Specifically, in a case of long length information with many bits needing to be processed, it is difficult to implement the integrated interleaver for similar reasons as the random interleaver.
Second, in a case where convolutional code uses the number of memories is 1 as an inner code, block interleavers included in the integrated interleaver may not support a sequential decoding operation, which is as an advantage of a convolutional code. Put another way, for this reason, an advantage of a signal receiving apparatus may not be supported, and as such, it may be difficult to implement the integrated interleaver.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present disclosure.